In next-generation high-definition medical diagnostic imaging devices, there is required an analog-to-digital converter that can realize an extremely high effective resolution of 18 bits or more at a conversion rate of 1 MS/s or higher. As such an ultrahigh resolution ADC, a sigma-delta ADC and a successive approximation ADC have been known.
In the case of the sigma-delta ADC, with employment of an internal quantizer of 1 bit, there is no need to provide a precision in an analog circuit. Also, with an increase in an internal operation clock frequency, a high effective resolution of 20 bits or more can be realized. However, in order to realize this high resolution, an over-sample rate of about 1000 times (internal operation clock frequency/conversion rate) is required. In the sigma-delta ADC, because an operational amplifier needs to operate at the internal operation clock frequency, an upper limit of the internal operation clock frequency becomes about 100 MHz due to a limit of its response speed. For that reason, in the sigma-delta ADC of 18 bits or more, the conversion rate remains at 100 kS/s or lower.
On the other hand, in the case of the successive approximation ADC, from the viewpoints that no over-sample operation is conducted unlike the sigma-delta ADC, and that no operational amplifier is required for an analog circuit part, there is a potential that the conversion rate higher than that of the sigma-delta ADC can be realized with the same effective resolution. However, in fact, the effective resolution depends on the rate precision of a capacitance value of each capacitive element configuring a DAC (hereinafter referred to as “internal DAC”) included inside the successive approximation ADC. In a related-art successive approximation ADC, in order to enhance a precision of the internal DAC, an element size of each capacitive element within the internal DAC, that is, the capacitance value is increased to reduce a rate precision variation among the respective capacitance values, thereby obtaining a necessary resolution. Because the conversion rate of the successive approximation ADC is reduced in inverse proportion to the capacitance value, in this method, the limit of the effective resolution is 16 bits at the conversion rate of about 1 MS/s.
For that reason, in order to obtain the effective resolution of 18 bits or more at the conversion rate of 1 MS/s or more, there is required a technology for improving the conversion rate and the effective resolution without increasing the element size of each capacitive element. This technology is disclosed in the following related-art documents.
W. Liu and Y. Chiu, “An equalization-based adaptive digital background calibration technique for successive approximation analog-to-digital converters,” International Conference on ASIC, pp. 289-292, October 2007, and W. Liu, P. Huang and Y. Chiu, “A 12b 22.5/45 MS/s 3.0 mW 0.059 mm2 CMOS SAR ADC achieving over 90 dB SFDR,” IEEE International Solid-State Circuits Conference Digest of technical papers, pp. 380-381, February 2010 discloses a digital correction successive approximation ADC in which the rate precision variation of the capacitance value in the internal DAC is compensated in a digital region so as to employ a small-sized capacitive element and a small capacitance value with the result that the effective resolution up to about 12 bits can be realized while increasing the conversion rate.
Also, Japanese Unexamined Patent Publication No. 2006-314035 discloses a technology by which, in a charge redistribution successive approximation ADC, sampling capacitive elements are connected in antiparallel to each other as a capacitive element pair to cancel a voltage first-order dependence of the capacitance value, and prevent the deterioration of the rate precision of the capacity as much as possible. JP-T-2003-504912 discloses a technology in which, in the capacitive elements within a general ADC, the capacitive elements are likewise connected in antiparallel to each other.